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Sutaone, M. S.
- CMOS Telescopic and Folded Cascode Amplifiers
Authors
1 Electronics and Telecommunication Department at College of Engineering, Pune-411005, IN
Source
Programmable Device Circuits and Systems, Vol 4, No 13 (2012), Pagination: 713-717Abstract
A single stage CMOS amplifier cannot give desired performance parameters. By placing a common source amplifier stage in cascade with common gate amplifier stage, a very useful and versatile amplifier circuit is formed [1]. This is known as Cascode configuration. The basic idea here is to combine high input resistance and large transconductance of common source amplifier with current buffering property of common gate amplifier. This cascode combination gives increased output resistance, multiplied DC gain but reduced bandwidth. The load for cascode amplifier is selected a current source made from a cascode pair and is known as telescopic cascode amplifier. As all the MOSFETs in telescopic cascode operate in saturation, the range of output voltage swing gets limited. The folded cascode amplifier is formed by using NMOS CS stage and folded PMOS CG stage both fed from single MOSFET current source and loaded by cascode current source. The objective of this paper is to discuss the advantages of folded cascode over telescopic cascode amplifier. [14]Keywords
Kirchhoff’s Current Law (Kcl), Common Source (Cs) Amplifier, Common Gate (Cg) Amplifier, Folded Cascode Telescopic Cascode.
- Design of 4-Bit Flash ADC Using TIQ Based Comparator
Authors
1 College of Engineering, Pune, IN
2 Electronics and Telecommunication Department, College of Engineering, Pune, IN
Source
Programmable Device Circuits and Systems, Vol 4, No 5 (2012), Pagination: 245-250Abstract
Analog-to-digital converters are the key components in modern electronic systems. Since signal processing in digital domain has widely being studied, designing an analog-to-digital converter has become more challenging for the researchers. In this paper, a novel flash analog-to-digital converter for low-power & high speed applications has been proposed by incorporating the threshold inverter quantization technique. The key idea of this technique is to generate 2n-1 different sized threshold inverter quantization comparators for an n-bit converter due to which the fast data conversion speed improves the operating speed and the elimination of ladder resistors leads significant reduction in the power consumption. The use of two cascaded inverters as a voltage comparator is the reason for the technique's name (TIQ). The voltage comparators compare the input voltage with internal reference voltages, which are determined by the transistor sizes of the inverters. Hence, we do not need the resistor ladder circuit used in a conventional flash ADC. Unlike the conventional flash ADC whose comparators are all identical in size, the TIQ based ADC has individual comparators in all different sizes. To construct an n-bit flash TIQ based ADC, one must find 2n-1 different inverters, each has different Vm value, and one must arrange them in the order of their Vm value. The gain boosters make sharper thresholds for comparator outputs and provide a full digital output voltage swing. The comparator outputs- the thermometer code-are converted to a binary code in two steps through the '01' generator and the encoder. The proposed 4 bit flash ADC using TIQ is designed using FAT tree encoder and simulated with the help of TANNER-EDA tool in 0.25 μm CMOS technology.Keywords
Flash ADC, TIQ Comparator.- Implementation of Iris Recognition on FPGA
Authors
1 Department of Instrumentation and Control, College of Engineering, Pune, IN
2 Department of Electronics and Telecommunication, College of Engineering, Pune, IN
Source
Programmable Device Circuits and Systems, Vol 1, No 5 (2009), Pagination: 82-88Abstract
Iris recognition is accepted as one of the most efficient biometric method. Implementing this method to the practical system requires specific image processing where the iris feature extraction plays a crucial role. The first step in recognition is iris localization which consists in finding the iris boundaries as well as eyelids. In iris recognition system the maximum time is required for localization. In the recognition process the image acquisition system and size of theimage is an important for accuracy and overall system performance. Most of image processing algorithms are computationally intensive, so it is desirable to implement them in high performance reconfigurable systems. Recently, Field Programmable Gate Array (FPGA) technology is appropriate target for the implementation of algorithms for image processing. In this paper iris localization and iris recognition algorithms are implemented in MATLAB first, then the attempt has been made to design and develop iris recognition algorithm on FPGA. In addition, some of the optimizations are proposed and analyzed. Proposed solution is applied to 150×200 size colored images acquired under realistic conditions (UBIRIS Database).